Worked solutionOne step at a time
Put every event on one time line
Measure time from the moment the clock edge reaches FF1. The clock tree takes 40 ps to reach FF1 and 60 ps to reach FF2, so FF2's edge lands at 20 ps: that is the skew.
Follow the new data
FF1's output changes 30 ps after its edge (clk→q), and the short wire adds 5 ps. The new value reaches FF2's input at 35 ps.
Check FF2's hold window
FF2 is still capturing the old value on its own edge. Its input must stay steady for the hold time after that edge, from 20 ps to 40 ps. The new data arrives at 35 ps, inside the window, so FF2 may capture garbage.
Where is the clock period?
Nowhere. Launch and capture happen on the same edge, so the hold equation has no T in it. The setup check is different: it compares this launch with the next edge, one period later.
Answer: B, add delay on the short path
The data is 5 ps too early relative to FF2's late edge, so make the path slower. A few buffers (10 ps here) turn hold slack from −5 ps into +5 ps, and setup still has about 200 ps of margin. This is exactly what hold-fixing in place-and-route does: it inserts delay cells on short paths.
What the reel showedThe numbers behind the animation
The reel animates one clock edge in slow motion (1 ps shown as 50 to 170 ms) and draws the timing diagram as it happens.
- The clock edge reaches FF1 at 0 ps and FF2 at 20 ps, down a longer branch of the clock tree.
- FF1's output changes at 30 ps and the new value reaches FF2 at 35 ps, inside FF2's hold window of 20 to 40 ps.
- With the clock on time at both flip-flops, the same pair has +15 ps of hold slack. The 20 ps of skew turns it into −5 ps.
- Stretching the period from 250 ps (4 GHz) to 2,500 ps (400 MHz) moves setup slack from +215 ps to +2,465 ps. Hold slack stays at −5 ps.
Wrong answersWhy each one is tempting
| Pick | What went wrong |
|---|---|
| A · slow the clock | Works for setup failures, so it is the reflex. Hold has no period in it. |
| C · raise voltage | "Faster fixes timing" is true for setup. For hold, faster data is the problem. |
| D · faster flip-flop | Same trap: a smaller clk→q makes the data arrive even earlier, −15 ps. |
Follow-ups an interviewer asks nextTry these before opening them
Could you fix it on the clock side instead?
Yes, if you can reduce the skew. Delaying FF1's clock by 5 ps or more (or making FF2's branch shorter) brings skew to 15 ps and hold slack to 0. But FF1's clock may also launch other paths, and shifting it moves their setup and hold too, so tools usually fix hold on the data path.
Why is a hold failure worse than a setup failure after tape-out?
A setup failure can be worked around by running the chip slower. A hold failure cannot: it does not depend on frequency, so silicon with a real hold violation is broken at every clock speed.
Which process corner do you check hold at?
The fast corner: fast transistors, high voltage, low temperature. That is where data paths are quickest and arrive earliest, so hold slack is smallest. Setup is checked at the slow corner.
Skew helped setup here. Can you use that on purpose?
Yes, that is useful skew: delaying the capture clock gives a long path more time. Each picosecond added to setup slack this way comes straight out of hold slack, so you need hold margin to spend.
