Worked solutionOne step at a time
Where dynamic power comes from
Every clock tick charges and drains the chip's switching capacitance. Each charge costs C·V² of energy, a fraction α of the nodes switch per cycle, and there are f cycles a second.
Calibrate to a 2005 desktop chip
Take 100 W at 4 GHz and 1.25 V. That fixes the effective switched capacitance.
Faster switching needs more voltage
A gate's delay is roughly C·V / I, and the drive current of a short-channel transistor grows as (V − Vt)^a (the alpha-power law). So the highest clock a voltage supports is:
Solve for 5 GHz: V rises from 1.25 V to 1.74 V, +39% for +25% clock.
Put the voltage back into the power
Both factors multiply.
Answer: B, the voltage must rise too
If the voltage could stay at 1.25 V, 5 GHz would cost only 125 W. It cannot: the transistors would not switch in time. The extra voltage enters squared, so power runs away from the clock. A 2005 air cooler handles about 130 W, which this model reaches at 4.29 GHz. That is the power wall.
What the model showedThe curve in the reel
The reel sweeps the clock with the same model (dynamic power only; leakage would make every number worse).
- 2 GHz needs 0.66 V and burns 14 W. 3 GHz: 0.91 V, 39 W. 4 GHz: 1.25 V, 100 W. 5 GHz: 1.74 V, 241 W.
- On a 112 mm² die, power density goes from 89 W/cm² at 4 GHz to 215 W/cm² at 5 GHz.
- The power curve crosses the 130 W cooler limit at 4.29 GHz and 1.38 V. Real chips of the time topped out a little below 4 GHz for the same reason.
Wrong answersWhy each one is tempting
| Pick | What went wrong |
|---|---|
| A · Longer wires | Wires matter for delay on a new design, but the same chip clocked faster keeps the same wires and the same C. |
| C · Bigger transistors | Nothing about the transistors changes when you raise the clock; only f and V move. |
| D · Memory can't keep up | True of real programs, but it caps the speed-up, not the power. |
Follow-ups an interviewer asks nextTry these before opening them
Why did chips go multicore instead?
Run the curve backwards. At 3 GHz the same core needs only 0.91 V and burns 39 W, so two cores at 3 GHz take 79 W, less than one core at 4 GHz (100 W), with 1.5 times the total cycles for parallel work.
Why not just lower the threshold voltage Vt?
Lower Vt lets a lower V reach the same clock, but subthreshold leakage grows exponentially as Vt drops, roughly ten times per 80–100 mV. Past a point the chip burns power while doing nothing.
Dennard scaling said smaller transistors keep power density constant. What broke?
Dennard scaling shrinks V with every node. Around 90 nm, V could no longer drop because of leakage and the threshold floor, so each new node added transistors and frequency without the V² saving, and power density climbed.
What do modern chips do with this curve?
Dynamic voltage and frequency scaling: they slide up and down the same V–f curve every few milliseconds, boosting one core briefly when the thermal budget allows and dropping voltage when idle.
